Cerebras is going public. Here's what a wafer-scale chip actually is.

Cerebras filed its S-1 last week. The numbers are eye-catching, $510M in 2025 revenue, a $20B compute deal with OpenAI, a rumoured $35B target valuation, and most of the coverage has been about those numbers. But the reason any of those numbers exist is a piece of engineering that is genuinely strange, and I think worth taking half an hour to actually understand.

Cerebras sells a chip the size of a dinner plate. Not a chip mounted on something the size of a dinner plate. The chip itself is roughly 21.5cm on each side, about 50 times the area of an Nvidia H100. It is, by a wide margin, the largest chip ever commercially produced.

The chip itself is roughly 21.5cm on each side, about 50 times the area of an Nvidia H100.

I want to walk through why anyone would build such a thing, how they actually manufacture it without it being a pile of defects, and what it changes about running a large model. Because the "bigger chip" framing undersells what's going on.

What a chip normally is

Here's the thing most people don't picture clearly. When you buy a GPU, the actual silicon die inside it is small, an H100 die is around 814 square millimetres, roughly the size of a postage stamp. That die is cut out of a wafer: a 30cm disc of silicon that the fab etches circuits onto. A single wafer produces dozens of dies. Each die gets cut out, tested, packaged, and sold as a chip.

The reason chips are small is yield. Silicon manufacturing has defects, tiny imperfections scattered randomly across the wafer. If your die is small, most dies will be defect-free and you throw away the bad ones. If your die is huge, nearly every die has at least one defect, and you throw away nearly everything. Economics forces chips to stay small.

To build something powerful, you then wire many small chips together. A modern AI training cluster is thousands of GPUs, each one a separate chip, connected through networking hardware. That networking is where a lot of the pain lives. Moving data between chips is slow and expensive compared to moving data inside a chip. A large language model training run spends a huge fraction of its time waiting for chips to talk to each other.

What Cerebras did

Cerebras asked an obvious-in-hindsight question: what if we just didn't cut the wafer up?

Their chip, the WSE-3, currently shipping, is a single piece of silicon containing 900,000 cores and 44GB of on-chip memory, all etched onto one 46,225 square millimetre square cut from a single wafer. No cutting into dies. No packaging into separate chips. No networking between chips, because there's only one chip.

The thing every semiconductor engineer immediately asks is: how on earth do you deal with defects? A wafer that size is guaranteed to have dozens of bad spots.

The answer is the clever bit. The WSE is built as a grid of small, identical tiles, think of them as tiny redundant units. When the wafer comes off the line, Cerebras tests every tile, identifies the bad ones, and uses a layer of reconfigurable wiring to route around them. The chip ships with some tiles marked dead and the rest wired into a working mesh. Because there are far more tiles than you need, losing a few percent to defects doesn't matter.

The metaphor I keep reaching for: imagine a city built as a perfect grid of blocks, where some blocks turn out to be unusable, so you just close those streets and route traffic around them. The city still works. You've designed for the defects rather than trying to eliminate them.

(The metaphor breaks down in one important place, in a real chip, the "streets" aren't generic, they're specialised communication fabric, and the routing is baked in at manufacturing time, not dynamic. But for picturing why the approach works, it holds.)

Why this matters for AI

Modern AI workloads are memory-bound and bandwidth-bound. That means: the chips themselves can do arithmetic far faster than they can get data in and out. When you're running a large language model, most of the time is spent shuffling model weights from memory into the compute units.

On a GPU cluster, this shuffling happens at several levels, each slower than the last:

1. Inside the chip, between compute units and on-chip cache, fast.
2. From the chip to its attached memory (HBM), slower.
3. Between chips in the same server over NVLink, slower again.
4. Between servers over InfiniBand, slowest.

A lot of the engineering effort in training modern models, things like tensor parallelism, pipeline parallelism, ZeRO, is really about minimising how often you have to cross those boundaries.

Wafer-scale integration collapses the hierarchy. Because the whole model lives on one chip, with 44GB of memory directly adjacent to 900,000 cores, communication happens at on-chip speeds throughout. Cerebras claims this translates into dramatically faster inference for models that fit, they've published numbers showing Llama 3.1 70B running at around 2,100 tokens per second per user, which is roughly an order of magnitude faster than GPU-based inference services.

This is the thing to hold onto: the WSE isn't faster because it has more transistors (though it does). It's faster because data doesn't have to leave the chip.

The catch

If the chip is so good, why isn't everyone using one? Two reasons.

First, fit. The WSE has 44GB of on-chip memory. That's a lot for a single chip, but it's not enough to hold, say, a 400B-parameter model in full precision. Cerebras handles this by streaming weights from external memory, which reintroduces the bandwidth problem they otherwise avoided. For models that fit entirely on-chip, the architecture is spectacular. For models that don't, it's less obviously a win.

Second, ecosystem. Nvidia's moat isn't just silicon, it's CUDA, PyTorch integration, thousands of optimised kernels, a decade of tooling, and the fact that every ML engineer alive already knows how to use a GPU. Cerebras has its own software stack, and while it's good, "good" is not the same as "the default thing everyone already uses". Adopting Cerebras means rewriting or recompiling significant parts of your pipeline.

This is why the OpenAI deal matters beyond the dollar amount. OpenAI has the engineering capacity to absorb that switching cost, and they run inference at a scale where the per-token economics justify it. For a smaller shop, the calculus is different.

What to watch

Three things I'd track from here.

Whether the inference-speed advantage holds as models get bigger. Cerebras's pitch is strongest for models that fit on one wafer. As frontier models grow past that, the company has to connect multiple wafers together, which brings back the inter-chip communication problem they were built to avoid. They have an approach for this (the CS-3 systems can be clustered), but clustering wafer-scale chips is newer territory than clustering GPUs and the performance story is less clear.

Whether custom silicon from the hyperscalers eats the same use case. Google's TPUs, Amazon's Trainium, and whatever OpenAI is reportedly building with Broadcom are all attempts to beat Nvidia on specific workloads. Cerebras is competing with those efforts, not just with Nvidia.

The OpenAI equity stake. If the reported 10% equity piece is real, it's a strong signal, OpenAI doesn't take equity in suppliers casually, but it also makes Cerebras partially captive to one customer, which is not where a public company wants to be. Watch the S-1 for concentration risk disclosures.

The IPO will price on the revenue and the OpenAI deal. But the thing that makes Cerebras interesting, to me, is the chip itself, a bet that the right way to speed up AI is not better networking between chips, but no networking at all.

Footnotes and links

Further reading

• [Paper]: "Wafer-Scale Deep Learning", Lie, Lauterbach et al., the original Cerebras architecture paper
• [Docs]: Cerebras Developer Documentation, the SDK and model support matrix
• [Explainer]: Fabricated Knowledge's teardown of the WSE-2 manufacturing process
• [Filing]: Cerebras Systems S-1, SEC EDGAR, filed 17 April 2026

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